1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which includes a sense amplifier for amplifying a weak signal.
In addition, the present invention relates to a semiconductor memory device such as DRAMs, and more particularly to a semiconductor memory device including an overdriving sense amplifier.
2. Description of the Related Art
Not only a large memory capacity, but also a low power consumption and a high speed operation are increasingly required of a dynamic random access memory (DRAM).
Besides, in general, an integrated circuit such as semiconductor memory has a sense amplifier for amplifying data read out of a memory cell.
FIG. 1 shows an outline of a memory core unit of DRAMs.
A plurality of rectangular memory cell arrays 2 are arranged in the memory core unit 1. Each of the memory cell arrays 2 is configured of a plurality of memory cells MC which are arranged vertically and horizontally. The memory cell arrays 2 are surrounded with sense amplifier rows 3 and sub word decoder rows 4 which are respectively arranged in the horizontal direction and vertical direction. Sense amplifier drivers 5 are arranged in regions in which the sense amplifier rows 3 and the sub word decoder rows 4 intersect (regions which confront the four corners of the memory cell arrays 2).
Word lines WL (hereinbelow, also individually termed "word lines WL0 and WL1") are connected to the memory cell arrays 2, arranged from the sub word decoder rows 4 on the upper sides of the memory cell arrays 2 as viewed in the figure. Besides, bit lines BL and BLB are connected to the memory cell arrays 2, and they are arranged alternately from the sense amplifier rows 3 on both the sides of the memory cell arrays 2 as viewed in the figure. The bit lines BL and BLB are complementary bit lines in which, when one of them is used for reading data, the other is set at a reference voltage. The sense amplifier rows 3 are controlled by the sense amplifier drivers 5 on the upper sides of these sense amplifier rows as viewed in the figure.
FIG. 2 shows the details of the memory core unit 1 and a peripheral circuit unit 15.
Each of the sense amplifier rows 3 includes a plurality of sense amplifiers AMP, precharging circuits 6, and nMOS transistors 7a, 7b, 7c, 7d. The bit line BL is connected to the corresponding sense amplifier AMP through the nMOS transistors 7a, 7b. On the other hand, the bit line BLB is connected to the corresponding sense amplifier AMP through the nMOS transistors 7c, 7d. A controlling signal BT1 is applied to the gates of the nMOS transistors 7a, 7c, while a controlling signal BT2 is applied to the gates of the nMOS transistors 7b, 7d.
The sense amplifier AMP has two CMOS inverters 8, 9. The input nodes and output nodes of the CMOS inverters 8, 9 are interconnected. A sense amplifier driving signal VP is applied to the sources of pMOS transistors 8a, 9a constituting the respective CMOS inverters 8, 9. Also, a sense amplifier driving signal VN is applied to the sources of nMOS transistors 8b, 9b constituting the respective CMOS inverters 8, 9. The output nodes of the CMOS inverters 8, 9 are respectively connected to the bit lines BL, BLB. By the way, in the following description, a pMOS transistor and an nMOS transistor shall be simply termed "pMOS" and "nMOS", respectively.
In order to operate the plurality of sense amplifiers AMP at high speed, wiring patterns for the sense amplifier driving signals VP, VN are widened, so that they have large load capacitance.
The precharging circuit 6 has the bit lines BL and BLB connected thereto, and is fed with a precharging signal PR and a precharged voltage VPR. The precharged voltage VPR is a voltage which is equal to one half of an internal supply voltage Vii. The precharging circuit 6 is a circuit which supplies the precharged voltage VPR to the bit lines BL, BLB, and which equalizes the bit lines BL, BLB.
The word lines WL0, WL1 are respectively connected to the gates of the cell transistors TR0, TR1 (both being nMOS's) of the memory cells MC0, MC1. The bit lines BL, BLB are respectively connected to the sides of the cell transistors TR0, TR1 opposite to the cell capacitors of the memory cells MC0, MC1.
The sense amplifier driver 5 includes a pMOS 11, the gate of which is fed with a sense amplifier activating signal SAB. The sense amplifier driving signal VP is outputted from the drain of the pMOS 11. Also included is an nMOS 14, the source of which is supplied with a ground voltage VSS. A sense amplifier activating signal SA is applied to the gate of the nMOS 14. The sense amplifier driving signal VN is outputted from the drain of the nMOS 14. The precharging signal PR is applied to the gates of nMOS's 12, 13 which are located centrally in the sense amplifier driver 5. The precharged voltage VPR is supplied to the source of the nMOS 12 and the drain of the nMOS 13.
The pMOS 11 and the nMOS 14 supply the internal supply voltage Vii and the ground voltage VSS to the respective sense amplifier driving signals VP, VN of large load capacitance, and they have high drivability in order to operate the plurality of sense amplifiers AMP at high speed. Consequently, the sizes of the pMOS 11 and the nMOS 14 are large.
On the other hand, the peripheral circuit unit 15 has a timing generator 16, a PR generator 17 for generating the precharging signal PR, and an SA generator 18 for generating the sense amplifier activating signals SA, SAB. This peripheral circuit unit 15 is formed in a region outside the memory core unit 1 shown in FIG. 1. Besides the above circuits 16, 17 and 18, pads, an input/output buffer, a main word decoder, a column decoder, or the like, which are not shown, are arranged in the peripheral circuit unit 15.
The timing generator 16 generates and outputs a precharging timing signal PRT which controls the precharging timing of the bit lines BL, BLB, and a sense amplifier timing signal SAT which controls the driving timing of the sense amplifier AMP.
The PR generator 17 receives the precharging timing signal PRT and a decoding signal WDEC of row addresses, and outputs the precharging signal PR which becomes a low level at the activation of the sense amplifier AMP.
The SA generator 18 receives the sense amplifier timing signal SAT and the decoding signal WDEC, and outputs the sense amplifier activating signals SAB, SA.
FIG. 3 shows the details of the SA generator 18.
The SA generator 18 is configured of a logic circuit 19 and four CMOS inverters 20, 21, 22, and 23. The logic circuit 19 is fed with the decoding signal WDEC and the sense amplifier timing signal SAT, and outputs signals SAB0, SA0 for activating the sense amplifier AMP. The activating signals SAB0, SA0 are signals whose phases are inverted from each other. The internal supply voltage Vii and the ground voltage VSS are respectively supplied to the sources of the pMOS's 20a, 21a, 22a, 23a and nMOS's 20b, 21b, 22b, 23b of the CMOS inverters 20, 21, 22, 23. The CMOS inverter 20 receives the activating signal SAB0 through the CMOS inverter 23, and outputs the received signal as the sense amplifier activating signal SAB. Likewise, the CMOS inverter 21 receives the activating signal SA0 through the CMOS inverter 22, and outputs the received signal as the sense amplifier activating signal SA. The sense amplifier activating signals SAB and SA are signals which become a low level and a high level at the activation of the sense amplifier AMP, respectively.
In the DRAM described above, for example, a read cycle is performed in order to read out data of high level written in the memory cell MC0 shown in FIG. 2.
FIG. 4 shows the timings of the principal signals in the read cycle.
Before the read cycle, the precharging signal PR is at a high level (a boost voltage VPP), the word line WL0 is at a low level (a resetting voltage VMI), and the sense amplifier activating signals SA and SAB are at the low level (the ground voltage VSS) and the high level (the internal supply voltage Vii), respectively. On this occasion, the timing generator 16 shown in FIG. 2 holds the timing signal PRT at a high level and the sense amplifier timing signal SAT at a low level. The boost voltage VPP is a voltage higher than the internal supply voltage Vii, while the resetting voltage VMI is a voltage lower than the ground voltage VSS.
During the high level of the precharging signal PR, the sense amplifier driver 5 turns on the nMOS's 12, 13, thereby to supply the precharged voltage VPR as the sense amplifier driving signals VP, VN. Also, during the high level of the precharging signal PR, the precharging circuit 6 supplies the precharged voltage VPR to the bit lines BL, BLB so as to equalize these bit lines BL, BLB. Accordingly, all the nodes of the sense amplifier AMP are at the precharged voltage VPR, so that the sense amplifier AMP is kept inactivated.
Thereafter, when address signals, a read/write signal or the like are inputted to the DRAM from outside, the DRAM starts the read cycle. The decoding signal WDEC is changed from a low level to a high level in accordance with the input of the row address signals. Besides, the timing generator 16 brings the precharging timing signal PRT to a low level and the sense amplifier timing signal SAT to a high level.
Upon receiving the precharging timing signal PRT, the PR generator 17 brings the precharging signal PR to the low level (VSS) (FIG. 4(a)). Subsequently, upon receiving the low level of the precharging signal PR, the precharging circuit 6 stops supplying the precharged voltage VPR to the bit lines BL, BLB so as to stop equalizing these bit lines BL, BLB. Then, the precharge operation of the bit lines BL, BLB is completed.
Upon receiving the low level of the precharging signal PR, the nMOS's 12, 13 of the sense amplifier driver 5 are turned off, thereby to stop supplying the precharged voltage VPR as the sense amplifier driving signals VP, VN.
Subsequently, the word line WL0 becomes the high level (VPP), and the cell transistor TR0 of the memory cell MC0 is turned on (FIG. 4(b)). The stored charges of the memory cell MC0 are shared by the bit line BL, and the voltage of this bit line BL rises (FIG. 4(c)). The bit line BLB is kept at the level of the precharged voltage PR, which is used as a reference voltage (FIG. 4(d)).
Subsequently, upon receiving the decoding signal WDEC and the sense amplifier timing signal SAT, the SA generator 18 shown in FIG. 3 brings the activating signal SAB0 to a low level and the activating signal SA0 to a high level. Further, the CMOS inverter 20 having received the low level of the activating signal SAB0 turns on the nMOS 20b, thereby to output the ground voltage VSS as the sense amplifier activating signal SAB (FIG. 4(e)). Likewise, the CMOS inverter 21 having received the high level of the activating signal SA0 turns on the pMOS 21a, thereby to output the internal supply voltage Vii as the sense amplifier activating signal SA (FIG. 4(f)).
Upon receiving the low level (VSS) of the sense amplifier activating signal SAB, the pMOS 11 of the sense amplifier driver 5 shown in FIG. 2 is turned on, thereby to supply the internal supply voltage Vii as the sense amplifier driving signal VP. Also, upon receiving the high level (Vii) of the sense amplifier activating signal SA, the nMOS 14 of the sense amplifier driver 5 is turned on, thereby to supply the ground voltage VSS as the sense amplifier driving signal VN.
The sense amplifier AMP is activated in accordance with the fact that the sense amplifier driving signals VP and VN become the high level and the low level, respectively. Then, the bit lines BL, BLB are differentially amplified until the voltage of the bit line BL is changed to the internal supply voltage Vii and that of the bit line BLB is changed to the ground voltage VSS (FIG. 4(g)).
The amplified voltage of the bit lines BL, BLB is transferred as an I/O signal through a column switch (not shown) which is controlled by the column decoder (not shown), and is outputted from the output buffer (not shown) to outside the DRAM.
Thereafter, the word line WL0 is brought to the low level (VMI), the sense amplifier activating signals SA and SAB are respectively brought to the low level (VSS) and the high level (Vii), and the precharging signal PR is brought to the high level (VPP) (FIG. 4(h)). Then, the sense amplifier AMP is inactivated, and the read cycle is completed.
Incidentally, also in case of a write cycle, the sense amplifier AMP is activated in the same way as in the read cycle. Besides, the bit lines BL, BLB are brought to the internal supply voltage Vii or the ground voltage VSS, thereby to write data into the memory cell MC0.
Meanwhile, the size dispersion of the sense amplifiers AMP needs to be prevented in order that data written in the memory cells MC may be accurately amplified by the sense amplifiers AMP. In the production of a semiconductor integrated circuit, there are a large number of fabrication processes which form the factors of size dispersion, and especially a lithography process is apt to incur the size dispersion. In the DRAM, the size dispersion of the sense amplifiers AMP becomes causes for the increase of an access time, the narrowed range of operating voltages, malfunctions, or the like, and seriously affects the yield of the manufactured articles of the DRAM. In general, therefore, the size dispersion is suppressed by setting the channel lengths, or the like of the constituent devices of each sense amplifier AMP to be greater as compared with those of the other devices.
This tendency holds true also of a product in which device sizes are made smaller every generation so as to achieve a reduced chip size and a heightened operating speed.
On the other hand, as shown in FIG. 1, the sense amplifiers AMP of the DRAM are constructed as the sense amplifier rows 3 and are arranged around the memory cell arrays 2. Therefore, when the sense amplifier rows 3 each being configured of the sense amplifiers AMP can not be accommodated on both the sides of any of the memory cell arrays 2, the number of the sense amplifiers AMP of the sense amplifier rows 3 is decreased in some cases. By way of example, on account of the decrease in the number of the sense amplifiers AMP, the sense amplifier row 3 at the right end is used to amplify the four memory cell arrays 2 on the left side.
As a result, the lengths of the bit lines BL, BLB connected to one sense amplifier AMP enlarge, and then increase the capacitance of these bit lines. Since the amplifying speed of the sense amplifier AMP lowers due to the increases in the bit line capacitance, the access time cannot be considerably shortened in spite of the product of reduced device sizes.
Here, the drivability of the sense amplifier AMP may be enhanced in order to shorten the access time without lowering the amplifying speed of the sense amplifier AMP.
As a method for enhancing the drivability of the sense amplifier, it is considered by way of example that the sizes of the pMOS 11 and nMOS 14 of the sense amplifier driver 5 shown in FIG. 2 are enlarged to enhance capabilities for feeding the sense amplifier driving signals VP, VN.
Since, however, the sense amplifier driver 5 is arranged in the intersecting region between the sense amplifier rows 3 and the sub word decoder rows 4 as shown in FIG. 1, it cannot be made larger than this region. It is accordingly difficult to enlarge the size of the sense amplifier driving circuit 5.
As another expedient for enhancing the drivability of the sense amplifier AMP, it is considered by way of example that the source of the PMOS 11 of the sense amplifier driver 5 shown in FIG. 2 is supply with a voltage higher than the internal supply voltage Vii, thereby to heighten the voltage of the sense amplifier driving signal VP.
The sense amplifier AMP, however, is activated also in the write mode. With this method, therefore, the voltage of the bit line BL becomes higher than the internal supply voltage Vii when data of high level is to be written into the memory cell MC0. In order to write into the memory cell MC0 a signal amount corresponding to the voltage of the bit line BL, the high level voltage for the word line WL0 must be set higher than the write voltage of the bit line BL by, at least, the threshold voltage of the cell transistor TR0. To heighten the high level voltage for the word line WL0, however, leads to degradation in the reliability of the gate insulator of the memory cell MC0. Moreover, it leads to increase in the power consumption of the chip to heighten the high level voltage of the bit line BL or word line WL0. It is accordingly very difficult and demeritorious to heighten the voltage of the sense amplifier driving signal VP.
On the other hand, in order to attain a lower power consumption, a recent DRAM generates an internal power supply lower in voltage than an external power supply and uses the lowered internal power supply as a power supply for memory cells, that is, the driving power supply of sense amplifiers. In other words, the high level of bit lines is set at the voltage (Viic) of the lowered internal power supply, whereby the driving power of the bit lines can be lowered to suppress voltages in the memory cells.
However, even when the internal supply voltage Viic is set low, the threshold voltages of the transistors of the sense amplifier or the like do not considerably differ from those in the prior art. Accordingly, the drivability of the sense amplifier lowers with the lowering of the internal supply voltage Viic, to incur the problem that the amplifying speed of the amplifier cannot be heightened. In order to solve such a problem, a sense amplifier of an overdriving system has been proposed.
FIG. 5 shows an example of the general configuration of DRAMs. A memory cell MC is configured of an NMOS transistor Qs and a capacitor Cs, and is arranged at the intersection area between a word line WL and bit lines BL, /BL. In the read or write operation of the memory cell MC, a sense amplifier SA detects and amplifies the small voltage difference between the bit lines BL, /BL. As described before, it is requested to lower the voltage of a cell power supply and to heighten the operating speed of the memory. The overdriving sense amplifier system has therefore been proposed as the drive system of the sense amplifier.
FIG. 6 is a timing chart showing the principle of the overdriving sense amplifier system. The precharge operation of the bit lines BL, /BL is performed in the standby state of the memory as explained below. First, owing to the activation (high level) of a bit line controlling signal brs shown in FIG. 5, the bit lines BL, /BL are connected through a transistor N6. Simultaneously, a precharged voltage VPR is supplied to the pair of bit lines through transistors N4, N5. The precharged voltage VPR in this example is set at 1/2 of the internal supply voltage Viic for the cell (that is, at 1/2 Viic).
When the memory becomes an active state, the bit line controlling signal brs is inactivated (low level), and a transfer gate controlling signal btl is activated (high level). Thereafter, the word line WL is selected (high level), a voltage corresponding to data held in the memory cell MC is transmitted to the bit lines BL, /BL, and the small voltage difference appears between the bit lines.
Sense amplifier activating signals lep, len are activated (to low and high levels, respectively) at the timing at which the voltage difference appears between the bit lines BL, /BL. Then, a driving voltage Viid is supplied to the sense amplifier SA. The driving voltage Viid is set at an external supply voltage Vdd which is higher than the internal supply voltage Viic. Accordingly, the sense amplifier SA is driven at high speed by the high external supply voltage Vdd, thereby to amplify at high speed the small voltage difference which has appeared between the bit lines BL, /BL.
The driving voltage Vdd of the sense amplifier SA is switched from the external power supply (Vdd) to the internal power supply (Viic) at the timing (a) in FIG. 6 at which the high level side of the bit lines BL, /BL has reached the voltage Viic. As shown in FIG. 6, the rising time and falling time of the bit lines BL, /BL become shorter in the case where the sense amplifier SA is overdriven (as a waveform indicated at symbol OD in the figure), in comparison with a case where it is not overdriven (as a waveform indicated at symbol NOD in the figure). In the former case, therefore, the read operation and write operation of the memory can be performed at high speed.
As explained above, in the sense amplifier SA of the overdriving system, the overdriving operation needs to be stopped by lowering the driving voltage of the sense amplifier SA at the timing (FIG. 6(a)) at which the voltage of the high level side of the bit lines BL, /BL has become the internal supply voltage Viic. In the prior art, the timing for stopping the overdriving is controlled by a timing signal which is generated by a CR delay circuit or the like.
FIG. 7 is a timing chart showing a problem involved in the prior art. The internal power supply (Viic) has been lowered in the memory, and has a stable voltage level. The external supply voltage Vdd for use as the overdriving voltage has a voltage fluctuation which is larger as compared with that of the internal supply voltage Viic. With the prior art method of stopping the overdriving by the time control of the delay circuit, therefore, the overdriving might be excessively applied as shown in FIG. 7 in a case where the sense amplifier SA is overdriven under the high level state of the external supply voltage Vdd. In this case, the sense amplifier SA is excessively driven, and the high level of the bit lines BL, /BL becomes as indicated by broken lines.
In such a case, the next precharge operation is performed in the state in which the voltage of the high level side of the bit lines BL, /BL has become high. In the precharge operation, a bit line precharging circuit BLPR shown in FIG. 5 operates. Owing to the operation, the pair of bit lines are short-circuited and come to have the precharged voltage VPR. Even when the high level voltage of the bit lines BL, /BL has increased to some extent, it can be lowered by a precharged voltage generator not shown. However, in a case where the increment of the high level voltage has exceeded the capability of the precharged voltage generator, the precharged level of the bit lines BL, /BL becomes higher than the voltage Viic/2 as indicated at a level V1 in FIG. 7. As a result, the bit line voltage on the high level side rises little in the subsequent read operation, to incur the problem that the data of the high level cannot be accurately read out.